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Altera_Forum's avatar
Altera_Forum
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15 years ago

create user IP with inside-fixed placement (like LogicLock)?

Hi, for a time-to-digit block i.e. Vernier delay line for pulse timing interpolation measurements, is there some way in Quartus Web Edition for creating custom user IP with a fixed inner relative pla...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks for pointers.

I tried to read up a bit more and Quartus doesn't seem to support Xilinx-style RLOC relative location constraints which'd make this very easy.

Though as you point out, via generate, and then maybe corner for absolute location start given as module parameters it seems well not entirely luxurious but at least more or less easily doable!