Forum Discussion
Altera_Forum
Honored Contributor
12 years agoSo when you are making such a fifo, you could use the dcfifo component.
Than there are all kinds of generics, most can be changed to the opposite value, but how about the other values? you could change delay_rdusedw to any natural value you like? Also there are some inputs and outputs ofcource, how would you know which ones you need and which ones you can leave out? I assume there must be some specification somewhere, am I right? When looking for it I only seem to get some other documentation I wasn't looking for, so I am probably using the wrong search terms. The pll component has a lot more ports and generics than the dcfifo:(