create megawizard components without megawizard

Thanks for your answer, I think you understood the question enough to give me an answer with value.

But what you say would sound like I am reinventing the wheel, since there already is a description and the megawizard only fills in these variable values. There are these tcl files, which I assume will take care of how the wizard generates that module. I have been writing in VHDL and this root file for the wizard is a .v file, so I don't like the tought I should change anything in the Verilog file. I might write something down what I didn't intent to be interpreted that way.