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Altera_Forum's avatar
Altera_Forum
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11 years ago

Create Generated clock in TImequest query

Hi Folks,

I am new to timequest analyzer and have read some of the info available from altera butr cant quite seem to generate the required clock.

I have a 1MHz PLL output which I divide down to 1KHz using a 500 count and toggle the output on each successive count.

In timequest I choose the PLL output as the source but when I select the toggle output as the target (by looking for the pin), timequest states there is no path between them and sticks in a 1MHz clock instead.

Do I need to select each bit in the count register as a target?

Or am i going about this completely in the wrong way?

thanks for any advice you can offer...

D

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Clocks can't go through registers. So if, for example, you had a series of ripple clocks(let's just say a chain of toggle flip-flops where the output of each one feeds the clock of the next toggle flop) then you need a generated clock on each toggle flop. I don't see this done, and instead user's have the main clock drive a counter. In this case all bits of the counter are driven by the clock, and only the LSB(or whatever bit you use as a clock) needs the create_generated_clock assignment.

    I'm not sure how the 1MHz clock came about. When you do a create_generated_clock, it takes that PLL clock and uses it for the generated waveform. Since it found the correct clock, and I assume you have a -divide_by 1000 option, then it should be able to get 1khz. The second thing it does is tries to find the path from the -source to the target. If it can't find that path, which would occur if there were other ripple clocks in between, then it should apply the correct clock waveform to the target, but it would just appear out of nowhere, i.e. the delay from the PLL to the target would not be used in timing analysis. (In some cases users use the divided down clock as a completely independent clock, in which case this is all right. Not ideal, but it works fine.) If it can find the connection, then during timing analysis you'll see the delays from the PLL to this new clock used when you do "report_timing -detail full_path..."