Create_generated_clock - Help with syntax

-source refers to your master clock

You should also specify the divide relationship and the duty cycle.

create_generated_clock -name <name> -source <source> -divide_by <ratio: 2,4,8, ....> -duty_cycle 50.00 <generated_clk>

<name> a name assigned to the generate clock to be used in TQ analysis

<source> the reference to your master clock

<generated_clk> in your case this is the lpm_counter port where you pick the generated clock from

Hi Cris,

thanks a lot for the reply.

A couple more questions if you don't mind please? . . . . . .

The counter allows me to pick of a number of sub-divided clocks, i.e., 32 --> 16, 8, 4, 2, 1 MHz

Do I need a generated clock for each, or just the counter itself?

clk is the name of the pin connected to the external 32MHz oscillator, its entry in the .SDC file is

create_clock -name clk -period 31.25 [get_ports clk]

the counter block is lpm_counter0

with an instance name of clock/2

the lpm_counter parameters are q[4..0],

can you tell me the exact syntax to enter, e.g., assuming that I need a generated clock for each . . . .

create_generated_clock -name <something> -source clk -divide_by 2 -duty_cycle 50.00 <what do I enter here to specify the counter port>

create_generated_clock -name <something_else> -source clk -divide_by 4 -duty_cycle 50.00 <what do I enter here to specify the counter port>

etc.

regards

Dave

The -name is whatever you want that makes sense. The target is the physical counter output. So most likely something like:

create_generated_clock -name divclk_16mhz -divide_by 2 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[0]}

create_generated_clock -name divclk_8mhz -divide_by 4 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[1]}

create_generated_clock -name divclk_4mhz -divide_by 8 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[2]}

create_generated_clock -name divclk_2mhz -divide_by 16 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[3]}

create_generated_clock -name divclk_1mhz -divide_by 32 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[4]}

Note that this is not recommended design practice. Even if they get put onto globals(in which case there won't be a lot of clock skew within the domain) there will be skew when passing data between these clocks. It could make timing closure difficult. If you're feeding a small amount of logic it's not a big deal, but something to watch out for. Having a PLL create these clocks is generally the recommended way. (Depending on the device, a PLL may not have access to that many globals, so you may need to drive regionals or something like that)

Hi Rysc,

thanks a lot for the reply, that seemed to work (after specifying -source clk in each case).

As pretty much a complete novice, the stuff about domains, globals and regionals went completely over my head I'm afraid.

But thanks also for following through and pointing out the error of my ways :-)

I have just found the explicit instruction in the Design Guidelines which says "To avoid glitches, do not decode the outputs

of a counter or a state machine to generate clock signals".

I guess that this is an example of how powerful, yet dangerous, the internet can be if you take as accurate information that you find there - ooops.

As a novice, I was looking for a way to divide my source clock into a number of sub-clocks for a Z80 based system that I am building - the EPM7128S will be doing the glue logic and I hoped to be able to use it to generate the sub-clocks that I need. So, I did a bit of surfing and came across an example of using an lpm_counter to generate the clocks, without realising that it was at odds with the design guidelines.

Referring to your comment about PLLs, am I correct in thinking that you are talking about using the ALTPLL megafunction?

Unfortunately, it is not implemented in the MAX CPLD.

Can you suggest another option to generate reliable sub-clocks from a master please?

regards

Dave

My follow up question about the correct way to dive the clock is a little "off topic" for my original question, so I have posted it in a fresh thread

http://www.alteraforum.com/forum/showthread.php?t=45218&p=186914#post186914

regards

Dave