Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi Rysc,
thanks a lot for the reply, that seemed to work (after specifying -source clk in each case). As pretty much a complete novice, the stuff about domains, globals and regionals went completely over my head I'm afraid. But thanks also for following through and pointing out the error of my ways :-) I have just found the explicit instruction in the Design Guidelines which says "To avoid glitches, do not decode the outputsof a counter or a state machine to generate clock signals". I guess that this is an example of how powerful, yet dangerous, the internet can be if you take as accurate information that you find there - ooops. As a novice, I was looking for a way to divide my source clock into a number of sub-clocks for a Z80 based system that I am building - the EPM7128S will be doing the glue logic and I hoped to be able to use it to generate the sub-clocks that I need. So, I did a bit of surfing and came across an example of using an lpm_counter to generate the clocks, without realising that it was at odds with the design guidelines. Referring to your comment about PLLs, am I correct in thinking that you are talking about using the ALTPLL megafunction? Unfortunately, it is not implemented in the MAX CPLD. Can you suggest another option to generate reliable sub-clocks from a master please? regards Dave