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Altera_Forum
Honored Contributor
11 years agoThe -name is whatever you want that makes sense. The target is the physical counter output. So most likely something like:
create_generated_clock -name divclk_16mhz -divide_by 2 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[0]} create_generated_clock -name divclk_8mhz -divide_by 4 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[1]} create_generated_clock -name divclk_4mhz -divide_by 8 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[2]} create_generated_clock -name divclk_2mhz -divide_by 16 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[3]} create_generated_clock -name divclk_1mhz -divide_by 32 {lpm_counter0:Clock/2|lpm_counter:LPM_COUNTER_component|dffs[4]} Note that this is not recommended design practice. Even if they get put onto globals(in which case there won't be a lot of clock skew within the domain) there will be skew when passing data between these clocks. It could make timing closure difficult. If you're feeding a small amount of logic it's not a big deal, but something to watch out for. Having a PLL create these clocks is generally the recommended way. (Depending on the device, a PLL may not have access to that many globals, so you may need to drive regionals or something like that)