Create false path within verilog source code. No access to SDC constraints.

Question

Hi there, I'm looking to create a false path constraint without the use of SDC constraints, as I do not have access to the constraints file. I've been looking around and have found the CUT attribute, but it does not appear to affect the timing analyzer nor create assignments. Am I just using it wrong?Below is the line in question. I intend to create a register that represents a de-facto constant for the duration of a run. It is only written to once during an "initialization" phase, and gets plenty of time to propagate to the entirity of the design (~1000 clock cycles before "run" phase begins). This value is very widely used, and making all paths starting from this register a false path would improve my FMax significantly.
(* altera_attribute = "-name CUT ON -to *" *) reg[127:0] topReg;
The equivalent SDC constraint I'd like to add but can't:
set_false_path -from [get_keepers ...|topReg]
 Any ideas?

sstrell · Answer

This isn't possible.  All timing constraints must be in a .sdc file.  If you don't have access to the "global" .sdc for your project, you can create a local .sdc and put constraints for just what you're working on in it.  If it's added to the project along with the global .sdc, local constraints can override what's in the global file.
"CUT" I don't even recognize and may be from way back before the current timing analyzer where timing constraints were set up as assignments for the project.

lennartvh · Answer

That's a shame, the problem is I'm developing a native module for my OpenCL project, and aoc doesn't accept .sdc files. Is it possible to bundle constraints into a verilog source file in any way?

sstrell · Answer

Do you mean you're building a custom BSP?  If so, then you should be able to include a .sdc with the BSP.  If not, meaning you're just designing a kernel, then you should not have to create timing constraints.  Running aoc should guarantee that you're meeting timing.

lennartvh · Answer

That's the thing, I am designing a kernel, but the core component is a verilog native module that is linked into it using aoc. OpenCL is used just for PCIE communication and memory management. I'm actually going a step further, (ab)using clock2x to get up to 600MHz. This is where meeting timing is quite a big challenge.

sstrell · Answer

This is not my expert area (and there is a separate forum for OpenCL), but it's up to the designer of the BSP to guarantee timing closure.  So whoever is building the Platform Designer system for OCL should account for the speed that the design is to run.

Forum Discussion

Create false path within verilog source code. No access to SDC constraints.

6 Replies

Recent Discussions

how to reduce clock skew between synchronous clock

Quartus 13.1 including Signal Tap License

I do not get an eMail with the generated license file

Installer cannot establish connection with SSL error

Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG