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LennartVH's avatar
LennartVH
Icon for New Contributor rankNew Contributor
4 years ago

Create false path within verilog source code. No access to SDC constraints.

Hi there, I'm looking to create a false path constraint without the use of SDC constraints, as I do not have access to the constraints file. I've been looking around and have found the CUT attrib...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

This is not my expert area (and there is a separate forum for OpenCL), but it's up to the designer of the BSP to guarantee timing closure. So whoever is building the Platform Designer system for OCL should account for the speed that the design is to run.