New Contributor
New ContributorThat's a shame, the problem is I'm developing a native module for my OpenCL project, and aoc doesn't accept .sdc files. Is it possible to bundle constraints into a verilog source file in any way?
Super ContributorDo you mean you're building a custom BSP? If so, then you should be able to include a .sdc with the BSP. If not, meaning you're just designing a kernel, then you should not have to create timing constraints. Running aoc should guarantee that you're meeting timing.
New ContributorThat's the thing, I am designing a kernel, but the core component is a verilog native module that is linked into it using aoc. OpenCL is used just for PCIE communication and memory management. I'm actually going a step further, (ab)using clock2x to get up to 600MHz. This is where meeting timing is quite a big challenge.
