Forum Discussion
Altera_Forum
Honored Contributor
12 years agopre-compiling wont give you any speed up - most of the compile time is taken in the fit and that will changing based on EVERYTHING and will have little to do with the underlying VHDL. The best thing to do is just put the files into a separate directory and put a .qip file in there. Then you can just include the .qip file in the next project.
For modelsim, you can compile the libraries locally into a work library, and then from the new project just use vmap to bring in the library: vmap my_pwm_library /code/pwm/work