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Altera_Forum's avatar
Altera_Forum
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12 years ago

create an include file in modelsim

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I am trying to create a macro file in modelsim. The file extension I need is .vh (Verilog include file). However, when I choose the file type as macro, I got a TCL file. Does anybody know how to create an include file with file extension of "vh"? Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    This is my initial guess too. However, after I added the search path in the "Verilog and System Verilog", I was still told the include file can't be found.

    Anybody knows how to solve the problem?