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Altera_Forum's avatar
Altera_Forum
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18 years ago

counter.v and tcounter.v simulation in ModelSim

Hi, I'm new to testbenches so I set a goal to get those Verilog examples to work under ModelSim. I'm trying to do the simplest of things - to run the counter.v and tcounter.v simulation an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

yep, when optimization is disabled it worked. Thanks much.

But why does this occur? And why doesn't optimization kill the objects if the source is VHDL?

It only seems to occur with Verilog source?

Thanks

~B