Forum Discussion
Altera_Forum
Honored Contributor
12 years agoMaybe I am not explaining myself in the better way :X
I have a DE0-nano FPGA that sends a pulse, a RADAR receive it and send it, and then I receive the echo signal in my ADC that is inside the FPGA (there is no DAC in this FPGA). My purpose is to measure the delay between the sending signal and the received signal in the ADC. My question is how can I do it in VHDL or maybe with DSP-Builder. Thanks