Counter implementation in Quartus II 7.2

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I would rather expect some T flip-flops.

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You can only build an asynchronous ripple-carry counter from T flip-flops, almost useless for fast logic design. Or do you see, how the below logic, that describes the said synchronous counter could use T-flip-flops? The adder ist exactly implementing the line result = result + 1;

always @(posedge clk or posedge reset)
  begin
    if (reset) 
      result = 0;		
    else if (ena) 
      result = result + 1;
  end