Counter design using QSYS & NIOS PROCESSOR?

Hi,

I am trying to implement 8-bit counter design using QSYS and NIOS Processor. please verify the design and tell me the modifications. I need to run the Counter design using QSYS & NIOS PROCESSOR.

I have verilog code for counter design but i dont know how to add its slave interface. So i am following the below procedure. Hope anyone help me in teaching me.

Thank you in advance

The steps i have

1. In QSYS, Integrated the Components in System contents, and Generated HDL and .bsf file

2. .bsf added in Block file of Quartus

3. BDF file made as Top level design (added .bsf)

4. Set pins

5. Compiled.

6. Then Launched NIOS

Counter code Logic

 module Eight_counter    (  out     ,  // Output of the counter  clk     ,  // clock Input  );  input clk;  output  out;  reg  out=0;    //-- Sensitive to rising edge always @(posedge clk) begin      // clock Input is L15 pin. How to set that pin in NIOS processore  out <= out + 1; end endmodule

NIOS PROCESSOR Code

# include "sys/alt_stdio.h"
# include<io.h># include<system.h># include<stdio.h>
# define COUT_BASE 0x3020
//#define IORD(COUT_BASE,OFFSET)
int main()
{
int i, count, data=0;
for(i=0;i<=7;i++)
{
    count=IORD(COUT_BASE,i);
    data=count + 2;
    printf("Result: %d\n", data);
}
return 0;
}

https://alteraforum.com/forum/attachment.php?attachmentid=15685&stc=1

Block design from Qsys

https://alteraforum.com/forum/attachment.php?attachmentid=15686&stc=1

NIOS_OUTPUT

https://alteraforum.com/forum/attachment.php?attachmentid=15687&stc=1