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Altera_Forum's avatar
Altera_Forum
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14 years ago

Counter Bug

Hi all, I am currently doing watchdog timer for my project. It consists of an 8 bit counter which reloads the user's value automatically when in timer mode, or stays at zero (in watchdog mode...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

why separate them? why not combine it like this? 


IF(CLRn='0')THEN                           
  underflow_pulse_out_1<='0';             
  underflow_pulse_out_2<='0'; 
ELSIF(rising_edge(CLK))THEN                
  undeflow_pulse_out_1<=underflow_pulse_in;
  undeflow_pulse_out_2<=underflow_pulse_out_1;
END IF;

Now, this is again only a code snippet (can you please post the whole file, then we can simulate/look at it (feel free to PM it). I assume the other two lines are outside a process?

If you were to reset the counter on just the underflow signal, then you will avoid the FF line of the counter. But we need the whole code to see where the problem actually is.