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No, no, I think you might have misunderstood.
These 4 signals are not actually fed into the counter clock input, but to the counter enable so that the counter decrements only when one of these pulses goes HIGH. The counter's clock gets its signal from the main clock signal. Sorry if I wasn't clear on this.
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Thats good - but it would make more sense to call the signals something other than _clk. How about _en, because they are not clocks.
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Sorry to repeat the question, does this mean that the FF value is normal?
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Yes. The behaviour is perfectly normal. Whether you actually want this behaviour is down to your spec and design.
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On a different note, I have 2 latches that are supposed to delay the signal by 2 clock edges, but I got only 1:confused: I am starting to wonder whether SignalTap is playing with me or maybe Cyclone II is going kaputt?
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It will be neither. It will problems with the design and your coding. The way you say latch - is it really a latch (like a transparent latch) or are they registers.
If you could post the code, we could help much more. The code doesnt look like its anything special really.
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