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Altera_Forum's avatar
Altera_Forum
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14 years ago

Counter Bug

Hi all, I am currently doing watchdog timer for my project. It consists of an 8 bit counter which reloads the user's value automatically when in timer mode, or stays at zero (in watchdog mode...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for replying. This is not the entire code (I am not allowed to put it out), but snippets of it:

counter_process:PROCESS(CLK,CLRn,load_cntr_gate_ff2,load_cntr_trigger_ff2)

BEGIN

IF(CLRn='0' )THEN

CounterValue<=(OTHERS=>'0');

ELSIF(rising_edge(CLK))THEN

IF(cntr_trigger_input='0' )THEN

CounterValue<=Reload_value;

ELSIF(cntr_gate_input='0')THEN

CounterValue<=CounterValue-1;

END IF;

END IF;

END PROCESS;

CNTR_gate_input <= NOT((base_clk) AND (initialised_value) AND (start_stop_signal) AND (WD_gate OR TMR_gate_hi

OR TMR_gate_lo OR TMR_gate_internal));

CNTR_trigger_input <= NOT ((initialised_value)AND(SW_trigger OR SyncTrigger OR load_init_value_register_ff2 OR

TMR_mode_underrun_ff2 OR HW_trigger OR WD_trigger_signal));

Somehow I managed to solve the underflow signal problem, but the I still remove the temporary FF value during transition from zero to the user's value.