--- Quote Start ---
Generate needs a begin
--- Quote End ---
no, not generally. A begin is only needed, if e. g. constants are defined within the generate.
The original generate example is correct except for the missing generate label.
See the exact syntax definition from VHDL spec for reference
--- Quote Start ---
generate_statement ::=
generate_label :
generation_scheme generate
[ { block_declarative_item }
begin ]
{ concurrent_statement }
end generate [ generate_label ] ;
generation_scheme ::=
for generate_parameter_specification
| if condition
label ::= identifier
--- Quote End ---
Syntax elements in square backets [] are optional.
Honored Contributor
