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Altera_Forum's avatar
Altera_Forum
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17 years ago

Correctly using generate statements?

I'm trying to make a register in VHDL real quick. I have a simple DFF that I'm accessing as a component like so: ARCHITECTURE Structure OF sixteenbitreg IS Signal output : STD_LOGIC_VECTOR(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Here is an example of a generate:

example_generate: for i in 0 to 31 generate

begin

example_inst: entity work.example(rtl)

port map

(

example_clk => clk,

example_rst_n => rst_n,

example_signal => output(i)

);

end generate;