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Altera_Forum's avatar
Altera_Forum
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17 years ago

Correctly using generate statements?

I'm trying to make a register in VHDL real quick. I have a simple DFF that I'm accessing as a component like so: ARCHITECTURE Structure OF sixteenbitreg IS Signal output : STD_LOGIC_VECTOR(...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

so it should be:

BEGIN

for i in 15 downto 0 generate

begin

reg: onebitreg PORT MAP(regIn(i),en,clock,output(i));

end generate;

regOut<=output;

END Structure;

That doesn't quite work, do I need an extra end?