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Altera_Forum
Honored Contributor
16 years agoSanmao,
I'm using multiple clocks from 1 pll in my desgin. Also have jtag and logic analyzer instance. All registers are being clocked by the pll derived clocks. Rysc, Thanks for the help - that worked. I don't understand why Timequest didn't capture the altera_reserved_tck when it converted my QSF file to the SDC file. I did find an interesting tidbit: I'm using SOPC and SOPC generates it's own SDC file. I opened up the file a moment ago to find this comment inside: <begin quote># **************************************************************# Timequest JTAG clock definition# Uncommenting the following lines will define the JTAG# clock in TimeQuest Timing Analyzer# ************************************************************** # create_clock -period 10MHz {altera_reserved_tck}# set_clock_groups -asynchronous -group {altera_reserved_tck} <end quote> I think Altera needs to examine the default settings of their conversion tools. So, now I get through recompilation/fitting/timequest with no errors pertaining to altera_reserved_tck --- but I get new timing errors having to do with: altera_internal_jtag~TCKUTAP I'm getting setup and hold violations in both fast and slow models. So, I will now attempt to determine if this is a clock and cut it from analysis the same with the altera_reserved_tck. My question is why doesn't Altera have a custom SDC or TCL command to generate these JTAG clocks for us? Or has someone found a script on the web site that Altera has created? Thanks guys for your help.... Bill