Forum Discussion
Altera_Forum
Honored Contributor
10 years ago --- Quote Start --- How are your designs captured? Are they written in VHDL or Verilog? If so, you can create a project in Quartus targeting your chosen device and add all your source files. Quartus will extract then hierarchy for you from the source files. Cheers, Alex --- Quote End --- Thanks, Alex Those were old designs prepared by schematic capture. (i.e. *.gdf files).