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Altera_Forum
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16 years ago

convert bdf file to vhd using maxplus2 library

Hi,

I am new to Altera and would simply like to convert a .bdf file to .vhd. Using primatives works but specifying generic chips such as 7404, 7408, 7432, etc seems to have problems because the names of entities and ports start with a numeral rather than a letter. My inputs and outputs to the chips begin with a letter in the name but the chips are defined in the library .../altera/10.0sp1/quartus/libraries/others/maxplus2/ with only numbers for the port and entity names. I have used "File->Create/Update->Create HDL design file from current file" to convert from bdf to vhd and it recognizes some of these problems and puts a "\" in front of some of the names but never any of the ports.

The .bdf and the generated .vhd files are attached

Using the linux version of altera 10.0sp1 on SUSE 11.3

(Linux 2.6.34.7-0.3-desktop x86_64)

Messages from "Create/Update->Create HDL design file from current file"# Warning: Found Altera-specific megafunction, primitive or component "7404" p, li { white-space: pre-wrap;# Warning: Design name for "7404_0" contains a number -- illegal for Verilog HDL and VHDL -- adding "\" in front of name# Error: Name "2" in design file .../testproj2.vhd contains illegal character for VHDL# Error: Name "1" in design file .../testproj2.vhd contains illegal character for VHD#Error: Can't elaborate top-level user hierarchy

I'm sure there must be a simple fix for this. Grateful for any advice.

Regards,

jake

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    can you try changing the port names on 7404_0.vhd and testproj2.vhd?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I had tried that. It also requires changing the entity name in 7404_0.vhd since the conversion didn't apply backslashes to that file. The problem is that I can't change the name of 7404 in the macrofunction instantiation at the end of 7404_0.vhd:

    b2v_inst : 7404

    If I leave it as 7404 I get the following error when running "Start Analysis and Elaboration":# Error (10500): VHDL syntax error at 7404_0.vhd(40) near text "7404"; expecting "(", or an identifier, or a sequential statement

    If I change it to \7404\ then I get the error:# Error (10482): VHDL error at 7404_0.vhd(40): object "7404" is used but not declared

    It appears I would have to rename the library function and at that point I knew I was doing something wrong since someone would have already made these changes.

    By the way, where is b2v_inst defined?

    Thanks much
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    i attached some modified files that contain ideas for 2 alternatives. one has a ton of escape characters to get the design to compile, the other would be commenting out the instance of 7404 and writing the HDL instead

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks much thepancake.

    Did you maybe attach the wrong files? They look like the originals.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Did you ever get this to work? I have similar problem using a 74191 counter in bdf converted to VHDL. Apparently, the converter doesn't know that the VHDL name should be "a_74191" and is located in library "....vhdl/altera/maxplus2.vhd". I still can't get the .vhd code to pass Analysis & Elaboration no matter what I modify.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    My problem was that a number of components were defined in the library (and apparently never used) with names starting with digits rather than a letter. I ended up defining my own entities and used names starting with letters. It doesn't look like that is your problem though since your counter name begins with a letter. Wish I could be of more help but I haven't used Altera for quite some time.

    Good luck