Contradictions between 2 DDR examples

The setup and hold you are referencing (0.9 and 2.7) do not refer to the setup and hold requirements at the input of the FPGA. It appears from the document they refer to the requirements of the downstream device on the transmit side. See the SDC code on page 14 for the output (transmit) side. So the formula you are referencing is incorrect for the input. The correct formulas are on slide 3.5 as shown in the training table of contents there:

input delay max = data trace max - clock trace min + tcomax

input delay min = data trace min - clock trace max + tcomin

The app note appears to be ignoring trace delay differences (this is typical; clock and data trace usually are matched so they cancel each other out) and calculating just tcomax and tcomin based on:

tcomax = tcomax(data) - tcomin(clock) = 2.8 - 2 = 0.8

tcomin = tcomin(data) - tcomax(clock) = 1.2 - 2 = -0.8

It's a little strange for me to see the delay due to the phase shift (2 ns) used as the tco for the clock path, but it does make sense as slide 3.5 says to get a tco with respect to the PHY's input clock instead of its output clock, and the code on page 15 indicates that the input delay is relative to the rising or falling edge.

Hope this helps.

#iwork4intel

Thanks sstrell,

In my real life case I'm interfacing my design to an RGMII PHY. The PHY has the internal clock shift function enabled.

I'm attaching the information from the PHY's datasheet.

How would you define the timing constraints in this case ?

Hi Sir,

Seems like you are facing additional issue on timing. Currently we serve forum case per area basis. For new issue, appreciated if you can open a new thread to get the support from Intel experts. Thank you.