--- Quote Start ---
For the issue of not receiving initial build up values until it settles, yes you can do that readily:
with avg and avg_final starting at zero(at reset)
if avg > 95 then
avg_final <= avg; -- update
end if;
signaltap does not require code change but is a tool that you need to learn and capture data from any node for display or saving into files. It is added to project through the quartus before compilation.
I assume your adc signal is a constant value but remember that adc signal may start with +/- values due to noise or step response and thus may average slowly up
--- Quote End ---
@kaz
I don't want to write specific value 95 because the range is not always 95mA to 105mA. It should be generalized because 95mA to 105mA is for specific voltage that I set in DAC. How can make it generalized?
Also, I am using the code in a different way and I am getting the values quickly but the values coming out are wrong. I am using the code as follows:
--use_average.vhdl file
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity use_average is
port (
clock: in std_logic;
reset: in std_logic;
channel_1_sample: in std_logic_vector(11 downto 0);
channel_2_sample: in std_logic_vector(11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0)
);
end;
architecture rtl of use_average is
signal average_1, average_2: std_logic_vector(11 downto 0);
begin
channel_1: entity work.average
port map(
sample => channel_1_sample,
average => average_1,
clock => clock,
reset => reset
);
channel_2: entity work.average
port map(
sample => channel_2_sample,
average => average_2,
clock => clock,
reset => reset
);
slv_value1 <= average_1;
slv_value2 <= average_2;
end;
The average block is as follows:
--average.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity average is
port (
sample: in std_logic_vector(11 downto 0);
average: out std_logic_vector(11 downto 0);
clock: in std_logic;
reset: in std_logic
);
end;
architecture rtl of average is
type type1 is array (1 to 255) of std_logic_vector(11 downto 0);
signal stage: type1 := (others => (others => '0'));
signal sub_result: signed(12 downto 0) := (others => '0');
signal sum: signed(19 downto 0) := (others => '0');
begin
process (clock, reset) begin
if (reset = '1') then
average <= (others => '0');
elsif (rising_edge(clock)) then
stage(1) <= sample(11 downto 0);
for i in 2 to 255 loop
stage(i) <= stage(i-1);
end loop;
sub_result <= resize(signed(sample),13) - signed(stage(255));
sum <= sum + sub_result;
average <= std_logic_vector(sum(19 downto 8));
end if;
end process;
end;
In the adc top level block, the use_average block is used as follows:
component use_average is
port (
clock: in std_logic;
reset: in std_logic;
channel_1_sample: in std_logic_vector(11 downto 0);
channel_2_sample: in std_logic_vector(11 downto 0);
slv_value1 : out std_logic_vector (11 downto 0);
slv_value2 : out std_logic_vector (11 downto 0)
);
end component;
inst_average : use_average
port map (
clock => clk,
reset => reset,
channel_1_sample => adc_a_1_temp,
channel_2_sample => adc_b_1_temp,
slv_value1 => slv_value1,
slv_value2 => slv_value2
);
adc_a_1_temp and adc_b_1_temp are the output signals coming from the adc block i-e:
data_in : in std_logic_vector (31 downto 0);
process (clk, reset)
begin
if (reset = '1') then
out_val=0;
adc_a_1_temp = 0;
adc_b_1_temp = 0;
elsif(rising_edge(clk)) then
case state is
when out_1 =>
if done='1' then
data_out <= addr0 & bits;
adc_a_1_temp <= data_in(11 downto 0);
state <= out_2;
when out_2 =>
adc_b_1_temp <= data_in(11 downto 0);
state <= idle;
endif;
end process
Is it okay If I use the code in the above way? Kindly let me know.
Thanks
Honored Contributor
