Constraint Qsys IP Addressable Memory Range

There are several ways to do this, possibly requiring another IP core instance.

One thing you'll find when using Qsys is you end up needing an awful lot of extra blocks which do nothing more than pass signals through in different formats. For example there is no simple way of splitting conduits in Qsys, you end up with an HDL file that takes the signals in and spits them out unchanged, but then a TCL wrapper that makes Qsys think the signals have been remapped into other conduits.

Anyway, back to your case. The simplest way is to use the "Address Span Extender" core in Qsys. It's located in "Basic Function\Bridge and Adaptors\Memory Mapped". If you set the "number of sub-windows" to 1, and the "enable slave control port" to false, you should be able to then simply set the slave address width to 31 bits (2GB), and the expanded master address width to 32bit (4GB). You can also set the "sub-window" offset to point to whatever address in the DDR you want address 0 in the slave to point to.

Alternatively, you could make your own core which has two Av-MM interfaces and one less address bit on the slave than the master.

Finally, possibly the simplest option, is to simply change your DDR controller so that it thinks the memory is only 2GB not 4GB. One way to do this is to half the data width in the memory parameters - in your top level design, you would then simply not bother connecting half of the memory modules data lines, effectively pretending it is a 2GB DIMM, though this would reduce your overall throughput.

Depending on the memory arrangement, you may instead want to change the "row address width" to be 1 bit less (again Qsys thinks the memory is 2GB), and in the top level tie the MSB address pin to 0. This keeps the full throughput by retaining the full data width.