Forum Discussion
ContributorConstraint clocks of SPI interfa
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
ContributorHi there, the generated clock constraints are ignored which causes your out/input delay constraint are invalid:
Seems that the pll_inst doesn't exist, so there is no source clock for the create generated clock constraint which causes the issue:
- anonimcs
Hi,
If you shared any media/link after eah line of yours, they're not visible. I opened this thread in 3 different web browsers to see what you've shared in this response, but I couldn't see anything.
The `pll_inst` in the .sdc file is just a name that I made up, just to make easy to use the PLL's clock output in the whole .sdc file (you can also see that in this line below in the .sdc).
set_instance_assignment -name corepll_inst|altpll_component|auto_generated|pll1 -to pll_inst
You said that the `pll_inst` does not exist, but I can clearly see the corepll component (with the name `corepll_inst`) in the project. The component itself used in the project can be found under "IP Catalog -> Library -> Basic Functions -> Clocks; PLL and Resets -> PLL -> ALTPLL " and it's also instantiated in my top level .vhd file. So there must be another reason why the `pll_inst` doesn't seem to exist..
