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anonimcs
Contributor
ContributorConstraint clocks of SPI interfa
Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
TingJiangT_IntelContributor
ContributorI see, I have got the email from Richard. If there is no more changes on the project in the email, I'll use this one for investigation.
anonimcsContributor
ContributorNo, there are no updates since my email on 8th of May. Please go ahead!
