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anonimcs
Contributor
ContributorConstraint clocks of SPI interfa
Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
TingJiangT_IntelContributor
ContributorHi there could you provide all the files of the project, and you can exclude you RTL(.v file) for confidentiality.
anonimcsContributor
ContributorThere you go! Please let me know if you need anything else.
In short, I added virtual clocks for the QSPI and SCLK1-6 outputs and added them in the same clock group with the pll clock in addition to what I've discussed with the user sstrell above
