Forum Discussion
anonimcs
Contributor
ContributorConstraint clocks of SPI interfa
Hi all, I have a design where I generate an SPI clock and send some data over the slave. The slave is an ADC with its own setup/hold time constraints. In these constraints, the slave data input SDI ...
Adding the pins of the Quad SPI IP did not work, but generating another clock like this and constraining the other QSPI ports wrt. this clock seems to work somehow
create_generated_clock -name {qclk_vclk} -source [get_pins {corepll_inst|altpll_component|auto_generated|pll1|clk[0]}] [get_ports {QSPI_CLK}]
sstrell
Super Contributor
Super ContributorCan you show the detailed path breakdown and more of your timing constraints? It's not clear why data is being launched on a falling clock edge in this analysis.
anonimcsContributor
ContributorHi,
I cannot show more of my timing constraints because there is simply nothing else...
But please see the pictures attached for the detailed paths and the corresponding waveform
