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Altera_Forum
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8 years ago

Constraining timing on configurable PLL output for a range of frequencies

Hi I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly. ...
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Altera_Forum
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8 years ago

Hi a_x_h_75

Thanks for your reply. Yes, the PLL does operate in the valid operating range for both input and output.

The input frequency (ref clk) to the PLL doesn't change. However, I am re-configuring the Output frequency from the PLL by changing

the clock multiplier and divider values in the PLL (M, N, C values).

So input frequency is fixed at 100 MHz but the output frequency can change to either 300 MHz or 25 MHz or some other frequencies in between.

MS