Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Constraining timing on configurable PLL output for a range of frequencies

Hi I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

If the logic in your design operates at 300MHz then it will work at 25MHz as well. There's no reason, indeed no way, to constrain it for a lower limit at well.

However, the PLLs are a different issue. These do have a minimum frequency at which they will operate. You also need to ensure that the parameters you set when configuring the PLL combined with the source frequency you're giving it don't end up trying to operate the PLL outside its limits.

Are you setting up the PLL for one frequency and then driving it with another? This is, potentially, going to cause issues.

Cheers,

Alex