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Erlend's avatar
Erlend
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4 years ago

Constraining signal on FPGA output

Hi I am currently working on a ADC driver interface and I have come across the following timing requirement for the chip-select signal. My sclk is running at 50MHz, 20ns time period. Notice that bo...
SyafieqS's avatar
SyafieqS
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4 years ago

Hi Erlend,


Any updates?


  • Erlend's avatar
    Erlend
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi, and sorry for the missing reply!

    I was thrown into another project temporarely and will come back to this problem during the next couple of weeks.