New Contributor
New ContributorHi Sstrell.
The following constraints applies for the driver clock and the n_cs output port:
# First, a 50Mhz clock is made by toggeling the clk_50 register in a 100MHz process. The 50 Mhz clock source is constrained as follows:
# Define 50 MHz clock source, derived from 100MHz clock
create_generated_clock -name CLK_50MHZ -source {*|pll1|clk[2]} -divide_by 2 [get_registers {*clk_50}]
# The 50 MHz clock is used for the driver logic and to drive the CS1_AD_CLK output FPGA pin
# Create virtual clock on SCLK output pin. This virtual clock is the referance point for Signals to and from the ADC.
create_generated_clock -name ADC_SCLK -source [get_registers {*clk_50}] -divide_by 1 [get_ports {CS1_AD_CLK}]
# The following constraint is a placeholder for the proper output constraint..
set_false_path -from * -to [get_ports {CS1_AD_NCS}]
Super ContributorFirst, I'm assuming CS1_AD_NCS is the output port for n_cs. As such, you should not have a false path on it (you do mention that's a placeholder). You should, however, have a false path on the clock output so it is not analyzed as a data output (should only be analyzed as a clock).
Then you need set_output_delay for n_cs to tie your output clock to the n_cs output. This is basically a source synchronous output interface. Assuming you're matching the trace lengths for the clock and n_cs, constraints might look like this:
set_output_delay -max 7 -clock [get_clocks ADC_SCLK] [get_ports CS1_AD_NCS] -clock_fall
set_output_delay -min -8 -clock [get_clocks ADC_SCLK] [get_ports CS1_AD_NCS]
