Constraining ripple clocks, clock mux output clocks, altddio output clock

Hi I have a design in which I send out (off chip) (inverted) "sysclk_out" from altddio. I do not use PLL as a source clock. I just use the incoming clock (sysclk_in) to drive the altddio.

a.) I could not find a way to constrain that output clock.

b.) Should I create a virtual clock (exact phase and frequency as "sysclk_ext") to constrain the output data ports? I could not find the -source to use in "create_generated_clocks"

d.) In other design I have a mux selecting incoming clocks, how should I use "create_generated_clocks" to constrain the clocks?

Thanks in advance.