Constraining Megafunction Outputs

The timing analysis you need to do is from register to register (or more generally, from keeper to keeper). When you do not register RAM block outputs, the read paths for the RAM block go from the RAM block's registered inputs to the first register after the RAM block output (which would also be after the combinational logic in your case). You should not be using max delays for these paths. Use proper clock constraint(s) and report the timing from the RAM input to the registers after the combinational logic. When you look at the details of the data arrival path, you will see that the timing goes through the RAM block through the Q outputs.