Honored Contributor
Honored ContributorI think you are mixing the purpose of .qsf assignments and .sdc constrains. Have you assigned clk to actual FPGA pin location and actual clk source? For now use Pin Planner from Quartus to assign actual FPGA pins to your top level ports, assign clk port to FPGA pin where is some clock source is connected (e.g oscillator).
After you assign pin locations your design should work (if your VHDL is good enough), even if Timequest will tell you that your design does not meet timing because tool will assume that you are running your design at 1GHz clock frequency and other stuff because there are no proper constrains. Once you fix pin locations assignments and see some leds blinking come back here and we will solve problems with .sdc.