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Altera_Forum
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17 years ago

Constraining internal logic?

I have a bug somewhere in my design that causes data loss. All I/O has properly been constrained and verified ok. When compiling in LAI (Logic Analyzer Interface) configuration in my design (so i can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Thanks for the suggestions Brad. I have found the issue (a Verilog issue). The bug went away except for very rare glitches which could be attributed to jitter. I will incorporate this in my SDC too.

Thanks,

/John.