Constraining internal logic?

Even with a large setup slack, you could have a hold violation (hold is independent of frequency). Most uncertainty is covered by guard bands in the timing models of devices older than 65 nm, but you might need some clock uncertainty for something like PLL jitter. If you have small hold slacks reported with no uncertainty, then your actual slack might be negative when accounting for everything like jitter and the uncertainty in the phase relationship between two PLL outputs.

You might have something asynchronous that you are not aware of. Run the Design Assistant and go through its warnings.

If you find no problems indicated by regular compilation warnings or Design Assistant warnings and have positive slack over process/voltage/temperature even for hold with uncertainty added for PLLs, then a service request is probably appropriate.