Constraining interface with multiply clocks

So basically the DDS 160 clock is not synchronous to fpga clock but is made so through the 40MHz signal.

Your tSU/tH are relevant to the latching clock (160). You are trying to tell fpga about this 160 clock which is not output by fpga

You can either declare a virtual clock or actually generate that clock from PLL for the sake of constraints only(this is legal).

Then your constraints will be correct but you might need to adjust if there is clock skew between fpga and dds as clock is not going with data.

I am not sure why you change phase to 180(you can do that if it helps timing).