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If I understood your design: you got 80MHz clock sourcing fpga. Then FPGA PLL generates 40MHz and 160MHz for DDS chip.
I will keep all 3 clocks in phase. And yes your constraints are correct. You can add multicycle of 2 setup/1 hold if indeed your generated signals are every two clock periods of latching clock.
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Maybe i wrote it too complicated ;p
1. FPGA got 80 MHz source clocking
2. FPGA PLL generates 80MHz signal for internal logic, and 40MHz 180 phase shifted clock for DDS synchro pin
3. DDS got its own 640/160 MHz clock that can be synchronized via 40MHz signal on SYNQ_in pin.
4. DDS timings 1.75ns/0ns are required for internal dds 160MHz signal.
I can see in timequest that when i add -multiply_by x on generated signal in waveform view its phase offset is gone. Anyidea why ? should i add after -multiply -invert or -phase instruction ?
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