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Honored Contributor
Honored ContributorConstraining interface with multiply clocks
Hi I got the following problem: FPGA is controlling DDS (AD9910) driver with internal clock sysclk running at 640 MHz. The spec says that dds control pins are sampled with sys_clk running 1/4 of...
Altera_ForumHonored Contributor
Honored ContributorIf I understood your design: you got 80MHz clock sourcing fpga. Then FPGA PLL generates 40MHz and 160MHz for DDS chip.
I will keep all 3 clocks in phase. And yes your constraints are correct. You can add multicycle of 2 setup/1 hold if indeed your generated signals are every two clock periods of latching clock.
