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Altera_Forum
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12 years ago

Constraining a source synchronous, SDR, center aligned Input

I'm running mad with this: I want to connect a Texas Instruments TLK2201 to my FPGA (Cyclone IV). This Ethernet-Serdes has got a Ten-Bit-Interface (TBI) with center aligned Data at 125MHz. The ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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OK, I tried this. With no effect.

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do you mean it did not pass timing or you are not happy with fpga skew? If it passes timing then you got no problem. If it didn't then you may resort to PLL but a speed of 125MHz(SDR) should not a problem I believe.