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Altera_Forum
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12 years ago

Constraining a source synchronous, SDR, center aligned Input

I'm running mad with this: I want to connect a Texas Instruments TLK2201 to my FPGA (Cyclone IV). This Ethernet-Serdes has got a Ten-Bit-Interface (TBI) with center aligned Data at 125MHz. The ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Hmmmmm, I just read "AN 251: Using PLLs in Cyclone Devices"

There is no word, that source-synchronous mode is supported by cyclone devices.

Is this the reason for the warnings? Can someone verify?