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Altera_Forum's avatar
Altera_Forum
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17 years ago

constrain sdram_controller in timequest

i've never used timequest before. And i want to constrain my design(a sdram_controller) using timequest. i've read quartus handbook and some other documents about timequest(TQ_Analysis_forum.ppt,Cons...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It's tough to tell from just this. First, how is sd_clk phase-shifted? From that we'll know the relationship to your non-phase-shifted clock and the default setup and hold requirements.

Secondly, when receiving data, is it the roundtrip delay of sd_clk going off chip, clocking data from the sdram, and then it coming back? Just making sure, since this looks like how it's constrained.