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How does the clock gate conversion play if the register already has an enable? I read somewhere that it only works if the enable is available, and I know many registers have an enable...
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I don't actually know.Maybe Quartus can merge the clock enable produced by gated clock conversion with the clock enables from your code. Or maybe not.You'll have to test it.
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I've implemented the clock control blocks using altclkctrl. I think it's working but I'm getting a troubling
warning.Info (176449): Merged following Clock Control Blocks Warning (176704): CLKCTRL has less registers on the enable (ena) path for some destinations, and consequently, it may have a slightly different behavior than expected
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It looks like Quartus is converting your multiple clock control blocks with a single one and using clock enables to achieve the desired behavior.The warning says that the behavior may be slightly different, but I suspect it just means timing may be slightly different.
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