Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Constrain delay of internal paths

Hi All, Here is my clocking setup. I have the main clock coming into a pin and then into a 1-to-1 PLL. The PLL output is tapped off to local routing. From that routing it comes out in a tree...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've never seen that message, so can't help much. I did see one other case with this where they were talking about it merging two clkctrl blocks in serial, not in parallel. Not sure if you removed the names, but maybe that's something to look into. Probably worth looking at the RTL viewer and Technology Map Viewer to get a good handle on what's going on. Good luck.