Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Constrain delay of internal paths

Hi All, Here is my clocking setup. I have the main clock coming into a pin and then into a 1-to-1 PLL. The PLL output is tapped off to local routing. From that routing it comes out in a tree...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

ssnyde27,

- Your clock gating logic is susceptible to producing clock glitches when you gate/ungate the clock. You should use a glitch free gating scheme.

- Modern ASIC synthesis tools can infer glitch free clock gating from clock enables.

- Quartus has the ability to convert clock gating into clock enables during synthesis.

Option 1: You can re-write your HDL using clock enables; then turn on automatic clock gating in your ASIC synthesis tool. This is, hands down, my preferred option if I have a modern ASIC synthesis tool to work with.

Option 2: Manually use glitch free clock gating modules in your design; for FPGA tests, provide a clock gating module that meets Quartus conventions and enable automated gated clock conversion.

Quartus convention for gated clocks, suitable for conversion.

http://quartushelp.altera.com/10.1/mergedprojects/verify/da/comp_file_rules_clock.htm